The present invention relates to processes for etching silicon to form macroscopic cavities within the interior of a silicon wafer, each cavity having at least one opening connecting to the exterior surface of the wafer.
A number of references teach the electrolytic etching of silicon in acidic solutions. For example, German Patent No. 3,324,232 to Foll et al. teaches an etching process whereby a number of honeycomb pattern of open cells are formed in the surface of a silicon wafer, thereby increasing its effective surface area.
U.S. Pat. No. 5,544,772 to Soave et al. proposes the fabrication of microchannel plate devices by light-assisted electrochemical etching of n-type  less than 100 greater than  silicon. The light-assisted electrochemical etching process described in the ""772 patent is applied only to n-type silicon, and a light source is required to generate surface charges so that etching may proceed.
As described, for example, in Lehmann et al., Formation Mechanism and Properties of Electrochemically Etched Trenches in N-Type Silicon, J. Electrochemical Society, Vol. 1-7, No. 2, pp. 653-659 (1990) and in U.S. Pat. No. 4,874,484, light-assisted electrochemical etching of n-type silicon produces deep channels perpendicular to the surface of the silicon. If the silicon surface is provided with pits at preselected locations, the channels form at the pits and hence at the same preselected locations. As described in these references, and in numerous other references, it has long been believed that the mechanism responsible for such selective etching limited its application to n-type silicon.
U.S. Pat. No. 5,997,713 to Beetz, Jr. et al. disclosed the successful application of controlled deep-channel etching to p-type silicon. In processes disclosed in the ""713 patent, the silicon surface is provided with pits at preselected locations with the result that channels are etched into the silicon body at the same preselected locations as the pits.
Propst et al., The Electrochemical Oxidation of Silicon and Formation of Porous Silicon in Acetonitrile, J. Electrochemical Society, Vol. 141, No. 4, pp. 1006-1013 (1994), discloses the formation of deep channels at random locations in a p-type silicon body using electrochemical etching with a non-aqueous, anhydrous electrolyte. This reference does not disclose processes for etching channels at preselected locations. Moreover, this reference emphasizes that the use of aqueous electrolytes results in formation of highly branched, porous structures rather than trenches, cavities or other non-branched deep structures. Similar teachings are found in Rieger et al., Microfabrication of Silicon by Photo Etching, The Electrochemical Society Proceedings, Vol. 94-361 (1994). U.S. Pat. Nos. 5,348,627 and 5,431,776 to Propst et al. relate to this same work.
Despite these and other efforts in the art, substantial needs remain for further improvements in processes for forming buried cavities in silicon elements. It would be desirable to provide a process for forming cavities in p-type silicon at preselected locations. P-type silicon wafers are fabricated in large numbers for use in manufacture of conventional silicon semiconductor devices. Therefore, p-type wafers are readily available at low cost.
It would be particularly desirable to produce silicon elements having a number of macroscopic cavities beneath the surface of the silicon element wherein the cavities are covered by a layer of monocrystalline silicon near an exterior surface of the element. Structures having a monocrystalline region overhanging a cavity would be desirable in standard silicon device processing to produce active and passive microelectronic structures. It is not possible to produce such structures using a single-etching process by the state-of-the-art processing methods described above. While it is possible to make such overhung cavities by combinations of standard processing methods and wafer bonding, these approaches are less efficient than a single-etching process would be, because they require additional processing time, equipment and materials.
Applications such as high-speed radio frequency (RF) electronics, e.g., those used in cellular communications, require microelectronic devices having silicon layers that are electrically isolated from the bulk wafer substrate. It is desirable, but not possible in current practice, to produce such layers by removing material between the silicon layer and the bulk of the wafer in a single process. Moreover, it is desirable to produce thin layers of silicon oxide, as could be produced by etching macrocavities beneath a layer of crystalline silicon, then subjecting the remaining silicon to thermal treatment in an oxygenated environment. Such layers can be produced, at present, by SIMOX processing where oxygen atoms are injected individually beneath the surface of a silicon body, but the silicon body is subject to radiation damage that is intrinsic to the SIMOX process.
Other technologies, such as inkjet printing, slow-release drug delivery systems, and miniature reagent supply/storage reservoirs for xe2x80x9clab-on-a-chipxe2x80x9d chemical analysis systems require a plurality of precisely placed reservoirs on a single chip. Under current techniques, such reservoirs are produced by etching wafers of diverse materials and bonding them to each other. It is desirable to produce such structures by a single process.
The processes used to etch voids in silicon heretofore have operated at relatively low etch rates, so that the dimensions of the voids increase at less than 1 xcexcm per minute. It would be desirable to form cavities at a faster rate to reduce the cost of the process.
Moreover, processes which require anhydrous electrolytes incur additional costs due to the precautions that must be taken to eliminate water from the solvents and to isolate the process from moisture in the environment. These processes incur further costs associated with purchase and disposal of the required organic solvents. It would be desirable to eliminate these costs by providing an aqueous etching method.
A method according to a preferred aspect of the invention begins with providing a p-doped silicon element having front and back surfaces. The method further includes the steps of forming a plurality of pits at preselected locations on the front surface of the element and subjecting the pitted silicon element to electrochemical etching. In the electrochemical etching procedure, the front surface of the element and a counter-electrode are maintained in contact with an electrolyte while maintaining the silicon element at a positive potential with respect to the counter-electrode. A patterned electrode provides electrical contact at the back surface of the element within discrete regions which are aligned with the pits of the front surface. The element is etched preferentially at the pits to form cavities beneath the wafer surface. The silicon body is maintained at a positive potential relative to the counter-electrode, and the electrochemical cell is operated at a constant current density throughout the etching process. Preferably, the current density is maintained at a value on the order of twenty times as large as the current densities typically used to etch p-type silicon. More preferably, the current density is maintained at a value between 0.05 and 0.9 amps/cm2, most preferably at a value of about 0.4 amps/cm2. As cell impedance decreases, the voltage is allowed to decrease so that the current density is maintained near a constant value.
The term xe2x80x9cp-doped siliconxe2x80x9d as used in this disclosure refers to silicon having an appreciable quantity of p-type dopants such as B, Al and Ga, which tend to form positively charged sites, commonly referred to as holes in the silicon crystal lattice. Desirably, the silicon element contains at least about 1014 and more preferably at least about 1015 atoms of p-type dopants per cubic centimeter. The silicon element therefore has an appreciable number of holes in the silicon crystal lattice. The p-type material may optionally include some n-type dopants as well as the p-type dopants, and its electrical characteristics may be p-type, n-type or compensated. Most typically, the material is doped only with p-type dopants, or with an excess of p-type dopants over n-type dopants, and hence exhibits p-type electrical conductivity with holes as the majority carriers.
This aspect of the present invention incorporates the discovery that when a p-doped silicon body is provided with pits at preselected locations in its exposed surface, electrochemical etching will proceed at these preselected locations. Most preferably, the silicon element is substantially monocrystalline silicon, such as a wafer of the type commonly used in a semi-conductor fabrication or a portion cut from such a wafer. Desirably, the exposed surface of the silicon element is a  less than 100 greater than  surface of the crystal.
According to a particularly preferred aspect of the invention, the electrolyte is an aqueous electrolyte which includes fluoride ions and a surfactant. The aqueous electrolyte desirably has a pH of about 1 to about 4, more desirably about 2 to about 4 and most desirably about 3 to about 4. Most desirably, the electrolyte includes an acid other than hydrofluouric and a fluoride salt as a source of fluoride ions. Whether the fluoride ions are added as HF or as salt, the resulting electrolyte contains some HF. The aqueous electrolyte desirably has an HF concentration at least 0.25 M and more desirably between about 0.25 M and 10 M. HF concentrations of about 1.5 M to about 2 M are most preferred. Inorganic acids and salts are preferred. For example, the electrolyte may include HCl and NH4F. This preferred aspect of the present invention incorporates the realization that the teachings of the art, to the effect that etching of the p-type silicon with an aqueous electrolyte will result only in a branched microporous structure, are incorrect.
The most preferred processes do not require either the expense of anhydrous processing or the expense and hazards associated with handling and storing liquid HF as a starting reagent.
Methods according to the foregoing aspect of the present invention can be used to fabricate structures with numerous macrocavities buried within p-type silicon elements. The cavities can be placed at any desired locations on the silicon element. Etching p-doped monocrystalline silicon according to the preferred processes of the invention produces macroscopic cavities buried within the body with a uniform layer of crystalline silicon overlying the macrocavity. The thickness of the layer can be controlled by the initial diameter of the pits etched into the front surface of the silicon element. The use of particularly preferred etching processes produces monocrystalline silicon bodies wherein at least a major portion of the volume below the layer of crystalline silicon has been etched away, effectively isolating the silicon layer from the rest of the silicon body. An etching process according to the present invention may also be used to fabricate a silicon body having a single macrocavity with an overhanging layer of crystalline silicon, with the macrocavity occupying a major portion of the planar area beneath the surface of the silicon body.